`include "../src/counter.v"

//Testbench para o contador
module counter_tb;

reg clk = 0;
reg rstN = 0;

wire [1:0] out;

always #1 clk = !clk;

initial $dumpfile("counter_tb.vcd");
initial $dumpvars(0, counter_tb);

counter c(clk, rstN, out);

initial begin
#2 rstN = 1;
#12 rstN = 0;
#4 $finish;
end

endmodule
